1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus that controls threshold voltage of MIS (Metal Insulated Semiconductor) transistor, and particularly relates to a semiconductor integrated circuit apparatus and electronic apparatus capable of controlling substrate voltage of fine-detailed MIS transistors operating at low power supply voltages.
2. Description of the Related Art
In recent years, methods of lowering power supply voltage are well-known as important methods for making semiconductor integrated circuits low in power consumption. However, by lowering the power supply voltage, fluctuations in threshold voltages of MIS transistors or MOS (Metal Oxide Semiconductor) transistors have a substantial influence on operating speed of semiconductor integrated circuits.
With regards to this problem, in the related art, circuit technology for making variations in threshold voltage small has been developed. For example, the operation described below is carried out using a leakage current detection circuit and substrate voltage circuit incorporated in a semiconductor integrated circuit. Namely, when the threshold voltage is lower than a target value, leakage current increases to more than a target value and the detected leakage current therefore becomes larger than a set value. As a result, the substrate voltage circuit operates and makes the substrate voltage Lower, and the threshold voltage is corrected to be higher. Conversely, when the threshold voltage is higher than a target value, leakage current falls to less than a target value and the detected leakage current therefore becomes smaller than a set value. As a result, the substrate voltage circuit makes the substrate voltage higher, and the threshold voltage is corrected to be lower. For example, see Document 1, Kobayashi, T. and Sakurai, T., “Self-Adjusting Threshold-Voltage Scheme (SATS) for Low-Voltage High-Speed Operation.” Proc. IEEE 1994 CICC, pp. 271-274, May 1994.
Further, as shown in FIG. 23, as a circuit configuration for a leakage current detection circuit, two NchMOS transistors M1n and M2n with gates both connected to a first current supply Mgp are connected in series, and drain potential Vbn of M1n is applied to the gate of leakage current detection NchMOS transistor MLn. The two NchMOS transistors M1n and M2n are then made to operate in the sub-threshold region so as to generate input potential Vbn of leakage current detection NchMOS transistor MLn. Leakage current detection ratio therefore does not depend on power supply voltage or temperature (see, Document 2: Japanese Patent Application Laid-Open No. HEI9-130232).
However, semiconductor integrated circuit apparatus of the related art has the following three problems.
First, leakage current detected by leakage current detection NchMOS transistor MLn is extremely small, in the order of a few pA to a few tens of pA. It is therefore extremely difficult to implement a constant current source where a minute stable current flows due to the influence of microscopic leakage currents due to defects in the processes of an MOS transistor and increases in the size of MOS transistors etc. In addition, the response to the substrate voltage control operation delays due to the delayed change in the drain potential of the leakage current detection NchMOS transistor MLn. This results in fluctuation in substrate voltage which presents a first problem.
A second problem is that, in Document 1 and Document 2, the leakage current detection circuit is always operating and is therefore always consuming power.
Further, in recent years, the operating speed of the power supply voltage changes according to the operating speed which presents a third problem that how the threshold voltage is to be set for a changing system clock frequency and power supply voltage appropriately has been a big problem.